/*-----------------------------------------------------------------------
							 \\\|///
						   \\  - -  //
							(  @ @  )  
+-----------------------------oOOo-(_)-oOOo-----------------------------+
CONFIDENTIAL IN CONFIDENCE
This confidential and proprietary software may be only used as authorized
by a licensing agreement from CrazyBingo (Thereturnofbingo).
In the event of publication, the following notice is applicable:
Copyright (C) 2012-20xx CrazyBingo Corporation
The entire notice above must be reproduced on all authorized copies.
Author				:		CrazyBingo
Technology blogs 	: 		http://blog.chinaaet.com/crazybingo
Email Address 		: 		thereturnofbingo@gmail.com
Filename			:		spi_receiver
Data				:		2013-02-21
Description			:		Receive SPI Data from mcu..
Modification History	:
Data			By			Version			Change Description
=========================================================================
13/02/21		CrazyBingo	1.0				Original
13/10/17		CrazyBingo	2.0				Original
-------------------------------------------------------------------------
|                                     Oooo								|
+-------------------------------oooO--(   )-----------------------------+
                              (   )   ) /
                               \ (   (_/
                                \_)
-----------------------------------------------------------------------*/ 
/***************************************************************************
	//mcu spi interface
	input			spi_cs,		//Chip select enable, default:L
	input			spi_sck	,	//Data transfer clock
	input			spi_mosi,	//Master output and slave input
	input			spi_miso,	//Master input and slave output	
***************************************************************************/

`timescale 1ns/1ns
module spi_receiver
	   (
		   //global clock
		   input	clk,
		   input	rst_n,

		   //mcu spi interface
		   input	spi_cs, 		//Chip select enable, default:L
		   input	spi_sck	, 	//Data transfer clock
		   input	spi_mosi, 	//Master output and slave input
		   //	output				spi_miso,	//Master input and slave output

		   //user interface
		   output	reg	rxd_flag,
		   output	reg	[ 7: 0 ] rxd_data
	   );

//-------------------------------------
//mcu data sync to fpga
reg	spi_cs_r0, spi_cs_r1;
reg	spi_sck_r0, spi_sck_r1;		//fsmc default 0; 8080 default 1; spi default 0;
reg	spi_mosi_r0, spi_mosi_r1;
always@( posedge clk or negedge rst_n ) begin
	if ( !rst_n ) begin
		spi_cs_r0 <= 1;
		spi_cs_r1 <= 1;		//chip select enable
		spi_sck_r0 <= 0;
		spi_sck_r1 <= 0;	//data transfer clock
		spi_mosi_r0 <= 0;
		spi_mosi_r1 <= 0;	//Master output and slave input
	end
	else begin
		spi_cs_r0 <= spi_cs;
		spi_cs_r1 <= spi_cs_r0;
		spi_sck_r0 <= spi_sck;
		spi_sck_r1 <= spi_sck_r0;
		spi_mosi_r0 <= spi_mosi;
		spi_mosi_r1 <= spi_mosi_r0;
	end
end
wire	mcu_cs = spi_cs_r1;
wire	mcu_data = spi_mosi_r1;
wire	mcu_read_flag = ( ~spi_sck_r1 & spi_sck_r0 ) ? 1'b1 : 1'b0;	//posedge of sck
wire	mcu_read_done = ( ~spi_cs_r1 & spi_cs_r0 ) ? 1'b1 : 1'b0;		//posedge of cs

//-------------------------------------
//sample signal, receive data
reg	[ 3: 0 ] rxd_cnt;
reg	[ 7: 0 ] rxd_data_r;
always@( posedge clk or negedge rst_n ) begin
	if ( !rst_n ) begin
		rxd_cnt <= 0;
		rxd_data_r <= 0;
	end
	else if ( mcu_cs == 1'b0 ) begin
		if ( mcu_read_flag ) 	//posedge of sck
		begin
			rxd_data_r[ 3'd7 - rxd_cnt[ 2: 0 ] ] <= mcu_data;
			rxd_cnt <= rxd_cnt + 1'b1;	//0-7-8
		end
		else begin
			rxd_cnt <= rxd_cnt;
			rxd_data_r <= rxd_data_r;
		end
	end
	else begin
		rxd_cnt <= 0;
		rxd_data_r <= rxd_data_r;
	end
end

//-------------------------------------------------
//output spi receive data and receive flag
always@( posedge clk or negedge rst_n ) begin
	if ( !rst_n ) begin
		rxd_flag <= 0;
		rxd_data <= 0;
	end
	else if ( mcu_read_done ) begin
		rxd_flag <= 1'b1;
		rxd_data <= rxd_data_r;
	end
	else begin
		rxd_flag <= 0;
		rxd_data <= rxd_data;
	end
end

endmodule

